%0 Conference Proceedings
%T Automatic Flat-Level Circuit Generation with Genetic Algorithms
%+ Faculdade de Ciências e Tecnologia = School of Science & Technology (FCT NOVA)
%+ Instituto Superior de Engenharia de Lisboa (ISEL)
%+ Center of Technology and Systems (UNINOVA-CTS)
%+ Departamento de Engenharia Eletrotécnica e de Computadores (DEEC)
%A Campilho-Gomes, Miguel
%A Tavares, Rui
%A Goes, João
%Z Part 3: Analysis and Synthesis Algorithms
%< avec comité de lecture
%( IFIP Advances in Information and Communication Technology
%B 11th Doctoral Conference on Computing, Electrical and Industrial Systems (DoCEIS)
%C Costa de Caparica, Portugal
%Y Luis M. Camarinha-Matos
%Y Nastaran Farhadi
%Y Fábio Lopes
%Y Helena Pereira
%I Springer International Publishing
%3 Technological Innovation for Life Improvement
%V AICT-577
%P 101-108
%8 2020-07-01
%D 2020
%R 10.1007/978-3-030-45124-0_9
%K Automatic topology generation
%K Genetic algorithm
%K Variable Length Chromosome
%K Digital circuit
%K Analog circuit
%K Ngspice
%K Amplifier
%Z Computer Science [cs]Conference papers
%X This paper describes a novel methodology to generate analog and digital circuits, autonomously, using the transistor (or other elementary device, e.g. resistor) as the basic elementary block – flat-level. A genetic algorithm is employed as the generation engine and variable length chromosomes are used to describe the circuit topology that evolves during the search. The circuit devices type and sizing are described by each gene of genetic algorithm. The automatic process starts with the circuit input and output specifications, and proceeds with the circuit topology and sizing evolution to meet those specifications, eventually, ending up with a novel topology. During the evolution, each generated circuit is electrically evaluated by a spice-like circuit simulator, i.e. Ngspice, using full model specifications - like BSIM3 for transistors - in a highly parallelized architecture built over a multi-thread model.
%G English
%Z TC 5
%Z WG 5.5
%2 https://inria.hal.science/hal-03741565/document
%2 https://inria.hal.science/hal-03741565/file/496588_1_En_9_Chapter.pdf
%L hal-03741565
%U https://inria.hal.science/hal-03741565
%~ IFIP
%~ IFIP-AICT
%~ IFIP-TC
%~ IFIP-TC5
%~ IFIP-WG
%~ IFIP-WG5-5
%~ IFIP-DOCEIS
%~ IFIP-AICT-577